Transistors such as nFET and pFET devices can be fabricated in a gate first process or gate last process. The gate last process is also known as “replacement metal gate” techniques. The replacement metal gate technique can be used when forming planar devices or 3D devices, e.g., FinFETs.
In replacement metal gate techniques, the nFET and pFET devices include several sacrificial layers which are removed to define a gate cavity where a replacement gate structure will subsequently be formed. Various layers of material that will constitute the replacement gate structure are formed in the gate cavity, with nFET and pFET devices having a different number of materials. As is understood by those of ordinary skill in the art, a nFET device typically has a greater number of materials than the pFET device. By way of example, for an nFET device, the following materials may can be used to fill the cavity: a high-k gate insulation layer, a first metal layer (e.g., a layer of titanium nitride), a second metal layer, (e.g., workfunction metal), a third metal layer (e.g., a layer of titanium nitride) and a bulk metal layer, such as aluminum or tungsten. This is compared to a pFET device which typically requires a high-k gate insulation layer, a single layer of titanium nitride, e.g., workfunction metal, and the bulk metal layer.
As the gate length of transistor devices decreases, the physical size of the gate cavity also decreases. For this reason, it is becoming physically difficult to fit all of the needed layers of material in the cavity for the replacement gate structure, particularly for nFET devices which require more layers than the pFET device. Also, as the devices scale downward, the fabrication processing are becoming more difficult.
For example, as gate lengths continue to decrease, voids or seams may be formed as the various layers of material are deposited into the gate cavity. Such voids or seams may result in devices that perform at levels less than anticipated or, in some cases, the formation of devices that are simply not acceptable and have to be discarded. Also, the reduced-size gate cavity makes it more difficult to scale the workfunction metal in the nFET devices, with tungsten. In addition, the presence of fluorine in the tungsten chemical vapor (CVD) deposition chemistry (e.g., WF6) can impact the nFET Vt and adversely impact nFET workfunction scaling. It has also become more difficult to control the workfunction metal (WFM) recess process, as little space is available for both n-type workfunction metal and barrier TiN deposition, followed by SOH (spin on hardmask) during the recess process. Accordingly, it becomes a challenge to fill the narrow gate, e.g., smaller cavity, with organic planarizing layer (OPL).